1. Technical Field
The present invention relates to a manufacturing method of a semiconductor element which has insulating layers for electric field relaxation that are located at edges of gates of P-type and N-type transistors and made thicker than gates in channel regions in order to reduce electric fields concentrated into the gate edges, and regions for electric field relaxation located to surround the insulating layers for electric field relaxation and drains. In particular, the invention relates to a manufacturing method of a semiconductor element that can optimize withstand voltage levels of P-type and N-type transistors individually by controlling impurity distributions in the regions for electric field relaxation.
2. Related Art
As a method to increase a withstand voltage level of a transistor by controlling a region for electric field relaxation to reduce an electric field in the vicinity of a drain, for example, a technique to form a region for electric field relaxation by heat treatment is known. JP-A-6-29313 is an example of related art. The steps of this technique are: performing wet etching to make a portion corresponding to a region for electric field relaxation of a silicon substrate have the surface orientation (111), implanting boron ions and performing heat treatment at about 1000 degrees centigrade before forming a P-type region for electric field relaxation.
In addition, a technique to reduce a element size by minimizing a length of the region for electric field relaxation is known in a case where a first region and a second region for electric relaxation are involved. This technique can make a element smaller by minimizing an overlapped amount of these two regions for electric relaxation and minimizing a region with a high impurity concentration which does not work effectively for electric relaxation generated parasitically in the overlapped region. JP-A-11-8388 is another example of related art.
According to the former related art technique mentioned above, some improvement of a withstand voltage level for a unipolar transistor can be expected according to the description of a method for manufacturing a P-type transistor. However, it is difficult to improve withstand voltage levels for both of P-type and N-type transistors at the same time although that is required when the P-type and the N-type transistors are formed complementarily. Therefore, in the case where P-type and N-type transistors are used complementarily, a problem that the usage of the voltage is limited to the one that is lower between the two arises.
Further, even if the latter related art technique mentioned above is employed, it is still difficult to improve the withstand voltage levels for P-type and N-type transistors at the same time. Thus the problem that the usage of the voltage is limited to the one that is lower between the two has not been solved.